The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2002

Filed:

May. 14, 1999
Applicant:
Inventors:

Thach-Kinh Le, Monte Sereno, CA (US);

Chakravarthy K. Allamsetty, Milpitas, CA (US);

Carl H. Carmichael, Campbell, CA (US);

Arun K. Mandhania, Milpitas, CA (US);

Donald H. St. Pierre, Jr., Nashua, NH (US);

Conrad A. Theron, San Jose, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 ;
U.S. Cl.
CPC ...
G06F 3/00 ;
Abstract

A system and method for reading back data from a programmable logic device (PLD). A clock offset table having one or more clock offset values is constructed. Each clock offset value indicates a relative clock cycle at which a selected bit read from the device is saved and sent to a host computer. The data is read from the PLD at a rate of one bit per readback clock cycle, and the readback clock cycles are counted as the bits are read from the device. When the count of readback clock cycles equals an offset, the bit is selected and saved.


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