The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2002
Filed:
Oct. 27, 1999
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A system and method for transferring data from a first clock domain to a second clock domain wherein a clock skipping technique is employed to maintain the same level of data throughput in the transmitting and receiving domains. In one embodiment, a plurality of serial data values are received from a device in the first clock domain and are stored in a plurality of flip-flops. The data values are clocked into the flip-flops, one value per flip-flop, at a first clock rate corresponding to the first clock domain. After a value is stored in the last flip-flop, the cycle is repeated and the previously stored values are overwritten. The data values are retrieved from the flip-flops after the values have had time to stabilize, but before they are overwritten. The values are retrieved at a second clock rate corresponding to a second clock domain and are transferred to a device in the second clock domain. If the clock rate in the first clock domain is greater than the clock rate of the second clock domain, one or more of the first clock pulses is periodically skipped, according to a predetermined pattern based on the ratio of the clock rates. Thus, the number of data values stored over a period of time is equal to the value retrieved over that period. If the clock rate in the first clock domain is less than the clock rate in the second clock domain, pulses of the second clock signal are periodically skipped to equalize the number of values stored and the number retrieved.