The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2002
Filed:
Dec. 28, 2000
Adam Aleksan Kablanian, San Jose, CA (US);
Deepak Sabharwal, Fremont, CA (US);
Virage Logic Corp., Fremont, CA (US);
Abstract
A compilable ROM architecture with enhanced performance characteristics, i.e., increased speed and lowered power consumption, wherein a plurality of memory locations are organized into one or more I/O blocks, each having a select number of bitlines. At least a portion of the data map in the ROM is manipulated so as to achieve a desired distribution of 0's and 1's such that the loading of 0's on the bitlines is reduced. In one exemplary embodiment, the data map is inverted per bitline, per I/O, or both. Output path circuitry is appropriately manipulated for accurate outputting of the original data. In another embodiment, the data is stored in the ROM using a scrambled addressing scheme wherein a portion of the row and column addresses is interchanged in order to minimize bitline loading of the binary 0's.