The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2002
Filed:
Apr. 28, 2000
Janardhanan S. Ajit, Sunnyvale, CA (US);
Hung Pham Le, San Jose, CA (US);
Exar Corporation, Fremont, CA (US);
Abstract
The present invention provides an ESD structure that can tolerate voltages at the I/O pin, or pad, higher than the voltage allowed for such technology. More particularly, the present invention provides an electrostatic discharge integrated circuit having a first and second NMOS transistor, a first and second voltage divider, a first and second steady state biasing circuit. The first NMOS transistor sinks electrostatic discharge current from an input/output pad to a ground source, the first NMOS transistor having a drain coupled to the input/output pad, and a gate. The first voltage divider has a node connected to the gate of the first NMOS transistor. The first steady state biasing circuit connects to the gate of the first NMOS transistor. The second NMOS transistor sinks electrostatic discharge current from the input/output pad to the ground source, the second NMOS transistor having a drain coupled to a source of the first NMOS transistor, and a source coupled to the ground source. The second voltage divider has a node connected to a gate of the second NMOS transistor. The second steady state biasing circuit connects to the gate of the second NMOS transistor.