The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2002

Filed:

Jun. 03, 2000
Applicant:
Inventors:

Sanjay Manohar Bhandari, Sunnyvale, CA (US);

Ramesh Selvaraj, Santa Clara, CA (US);

Joao Nuno V. L. Ramalho, Bieville-Beuville, FR;

Patrick LeClerc, Caen, FR;

Eric Pieraerts, Caen, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11B 2/736 ; G11B 5/02 ; G11B 5/09 ;
U.S. Cl.
CPC ...
G11B 2/736 ; G11B 5/02 ; G11B 5/09 ;
Abstract

A preamplifier for a multi-head disk drive includes a circuit that tests the connectivity of each magnetic head in the disk drive by driving each head with a small current, and detecting the flow of this current. By driving and sensing the current flowing through the magnetic heads, both open-circuit faults and bridging faults can be detected. In a preferred embodiment, each head is tested sequentially. The result of each test is stored as a bit value in a register, for subsequent access. The circuit may be activated by a test device, or by a microcontroller in an assembled disk drive. To minimize costs, the circuit is integral to the circuitry that is conventionally used to read and write information via the magnetic heads. The oscillator that is conventionally used to characterize the read heads of a disk drive is used in a preferred embodiment to control the sequencing of tests through each head. A very low common mode voltage is provided during the testing of each write head, to minimize ESD (electro-static discharge) related problems. In a test mode, each write head is selected after a read head is selected, thereby minimizing the possibility of an accidental corruption of the data when the write head is tested. To avoid a degradation of performance, and in particular a degradation of rise/fall times in the write driver, the circuitry that controls the test voltages and currents is provided substantially up-stream of the write driver.


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