The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2002
Filed:
Nov. 27, 2000
Willem Hendrik Groeneweg, Muri, CH;
Koninklijke Philips Electronics, N.V., Eindhoven, NL;
Abstract
A FIRDAC ( ) is described, coupled to a noise-shaper ( ) with a DC offset. The resulting offset of the FIRDAC itself is compensated by a compensation current source (P ; N ) which is continuously ON. The FIRDAC has a plurality of FIRDAC cells ( ), each cell comprising at least one current source ( ). In a FIRDAC cell having a relatively small current source, a dummy transistor ( ) is formed in the free space. The compensation current source is formed as a parallel combination of certain dummy transistors. In a possible embodiment, each FIRDAC cell( ) comprises a stack comprising a D-flipflop ( ), a PMOS current mirror ( ) above the flipflop, and an NMOS current mirror ( ) below the flipflop. In a cell with relatively small PMOS and NMOS current mirrors, a dummy current mirrors ( ) are formed in the substrate ( ). A plurality of these dummy current mirrors ( ) are connected in parallel to constitute said compensation current source (N , P ).
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile