The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2002
Filed:
Oct. 28, 1996
Donald M. Bartlett, Ft. Collins, CO (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A CMOS negative voltage generator is provided which uses N-well technology. A positive voltage generator charges a load capacitor to a doubled voltage level. A first cycle of operation charges an output capacitor to a potential equal to the difference between the doubled voltage and the original voltage source. A second cycle of operation references the previously positive reference node of the output capacitor to ground level, and lets the negative node of the capacitor float to a potential equal in magnitude to the original power source, however now being negative with reference to ground. The negative voltage generator is ideal for driving a low impedance p-channel MOSFET. The negative voltage generator is ideal in low voltage circuits, including those with three volt supplies.