The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2002
Filed:
Mar. 24, 1999
Applicant:
Inventors:
Akira Yamamoto, Takatsuki, JP;
Shiro Sakiyama, Kadoma, JP;
Hiroyuki Nakahira, Katano, JP;
Masaru Fukuda, Hirakata, JP;
Akira Matsuzawa, Yawata, JP;
Shiro Dosho, Ikeda, JP;
Shinichi Yamamoto, Hirakata, JP;
Assignee:
Matsushita Electric Industrial Co., Ltd., Kadoma, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03D 3/00 ;
U.S. Cl.
CPC ...
H03D 3/00 ;
Abstract
A frequency-voltage conversion circuit receives a clock CLK as an input and provides a voltage IV in accordance with the frequency of the clock as an output. The input and output characteristic of the frequency-voltage conversion circuit is adjusted to substantially match a given input and output characteristic.
Yamamoto, Akira. (2002). Frequency-voltage conversion circuit, delay amount judgement circuit, system having frequency-voltage conversion circuit, method of adjusting input/output characteristics of frequency-voltage conversion circuit, and apparatus for automatically adjusting input (U.S. Patent No. 6424184). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6424184
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile