The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2002

Filed:

Feb. 20, 2001
Applicant:
Inventors:

Fumihiko Sato, Tokyo, JP;

Hiroyuki Takahashi, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/9094 ; H03K 1/9096 ;
U.S. Cl.
CPC ...
H03K 1/9094 ; H03K 1/9096 ;
Abstract

A logic circuit ( ) having a critical path input signal (C ) that can have a reduced input capacitance and a logic output (D ) that can have a reduced voltage swing is disclosed. According to one embodiment, the logic circuit may include an input circuit ( ), a driver circuit ( ), and a load circuit ( ). Driver circuit ( ) can include stacked transistors (N and N ) of the same conductivity type, which can generate a logic output (D ) that can have a reduced voltage swing. Driver circuit ( ) can generate a feedback signal that can control the impedance of a load circuit ( ). Load circuit ( ) can be actively controlled to improve the response of a logic evaluation node (V ).


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