Transistor, transistor array and non-volatile semiconductor memory

Abstract

A memory cell in a simple structure having a long life, less variations in the structure and writing characteristic, and a higher operation speed, free from the problem of over-erasure, and permitting down-sizing is disclosed. Floating gate electrodes are arranged on a channel region with a gate insulating film therebetween. A control gate is formed on the floating gate electrodes with a tunnel insulating film therebetween. A central part of the control gate electrode is provided on the channel region to form a select gate. Source/drain regions having the select gate therebetween and the select gate form a select transistor. The coupling capacitance between each of the floating gate electrodes and the control gate electrode is set much larger than the coupling capacitance between each of the floating gate electrodes and the substrate.