The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2002
Filed:
Dec. 15, 1999
Ming-Jang Lin, Taichung Hsien, TW;
Chorng-Wei Liaw, Yun-Lin Hsien, TW;
Tian-Fure Shiue, Hsinchu Hsien, TW;
Ching-Hsiang Hsu, Hsinchu, TW;
Huang-Chung Cheng, Tainan, TW;
Analog and Power Electronics Corp., Hsinchu, TW;
Abstract
A method for manufacturing a trench gate structure of a power metal-oxide-semiconductor field-effect transistor. A substrate is provided, which substrate has a epitaxial layer thereon, a base region formed in the epitaxial layer, a source region formed in a portion of the base region, a first dielectric layer on the base region and the source region, a second dielectric layer on the first dielectric layer and a trench penetrating through the second and the first dielectric layers, the source region and the base region and into the epitaxial layer. A third dielectric layer is formed on the bottom of the trench. A conformal gate oxide layer is formed in the trench. A conformal polysilicon layer is formed on the second dielectric layer and in the trench. A fourth dielectric layer is formed on the polysilicon layer to fill the trench. Portions of the fourth dielectric layer and the polysilicon layer are removed until the surfaces of the fourth dielectric layer and the polysilicon layer are substantially level with the surface of the base region.