System management mode circuits, systems and methods

Abstract

An electronic system ( ) includes a first integrated circuit (IC) ( ) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ ), and a logic circuit ( ) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate ( ) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate ( ) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN). A second integrated circuit ( ) has a system management interrupt (SMI#) output pin and SMI circuitry ( ) including a SMI register ( ) connected to events sources eligible for SMI response including the card SMI output of the first integrated circuit. This second IC ( ) further has a mask SMI register ( ) connected to the SMI register ( ) to select particular ones of the events sources for SMI response. A logic circuit ( ) is fed by the SMI register ( ) for combining the selected events sources to supply an internal SMI output (SMIOUT). Other circuits, systems and methods are also disclosed.