The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 16, 2002
Filed:
Mar. 04, 1999
Glenn A. Dearth, Groton, MA (US);
George R. Plouffe, Jr., Bradford, MA (US);
David M. Kaffine, North Billerica, MA (US);
Janet Y. Zheng, Andover, MA (US);
Sun Microsystems, Inc., Palo Alto, CA (US);
Abstract
A system and method for circuitry design verification testing using a structure of interface independent classes to provide for rapid prototyping and design modification while maximizing test code re-use. A circuit simulation subsystem is interfaced with a test subsystem. The test subsystem employs a system transaction class for collecting common routines and pointers to device transactions. One or more configuration transaction classes derived from the system transaction class define transactions between functional models within the simulation subsystem and cause instantiation of the respective functional models. Operations are performed on the functional models via pointers to interface independent transaction classes which define interfaces to the devices. The operations are mapped to the current designs of the functional models by subclasses of the interface independent transaction classes. Changes to the functional model designs necessitate changes to the subclasses, but the interface independent transaction classes maintain a consistent interface and allow the test code to be re-used with minimal changes.