Phase-difference detector and clock-recovery circuit using the same

Abstract

A phase-difference detector which uses a clock signal whose frequency is half the data rate, receives data at both rise timing and decay timing of the clock signal, and outputs phase-difference information between the data input signal and the clock signal. The detector has a circuit that comprises first and second register circuits for receiving a data input signal in synchronism with the decay timing and rising timing of the clock signal, respectively; a first exclusive OR circuit with two input terminals connected with the data input and the output terminal of the first register circuit; a second exclusive OR circuit with two input terminals connected with the outputs of the two register circuits; a first AND circuit for calculating the logical product of the inverted signal of the output of the first exclusive OR circuit and the inverted signal of the clock signal, and for producing a “down” signal; a second AND circuit for calculating the logical product of the output of the first exclusive OR circuit and the inverted clock signal; a third AND circuit with two input terminals connected with the output terminal of the first exclusive OR circuit and the inverted signal of the clock signal; and an OR circuit for calculating the logical result of the outputs of the second and third AND circuits, and for producing an “up” signal.