The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 16, 2002
Filed:
Apr. 09, 2001
Hideshi Maeno, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
To provide a semiconductor integrated circuit having a redundancy-relieved data output function which can carry out a pass/fail test of a selecting operation of a redundancy-relieved output selecting circuit for redundancy-relieved output data. Data inputs D of scan flip-flops SFFC <i+3>, SFFC <i+2>, SFFC <i+1> and SFFC <i> are connected to redundancy-relieved output data XDO <i+3>, XDO <i+2>, XDO <i+1> and XDO <i> in place of output data DO <i+3>, DO <i+2>, DO <i+1> and DO <i> of a conventional RAM , respectively. An AND gate receives a serial output SO <i+4> at one of inputs and receives a selector test signal PFIN at the other input, and an output thereof is sent to the other input of an AND gate . AND gates to to be connected in series receive serial outputs SO <i+1> to SO <i+3> of the SFFC <i+1> to the SFFC <i+3> at inputs, respectively.