The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 16, 2002
Filed:
Feb. 24, 2000
Samsung SDI Co., Ltd., Kyungki-do, KR;
Abstract
A field emission display includes first and second substrates spaced apart from each other with a predetermined distance. The top surface of the first substrate faces the bottom surface of the second substrate. A main cathode electrode layer is disposed on the top surface of the first substrate. A gate electrode layer is arranged over the main cathode electrode layer such that the gate electrode layer and the main cathode electrode layer intersect to be orthogonal to each other. The intersection of the gate electrode layer and the main cathode electrode layer becomes to be unit pixel areas. The gate electrode layer has a plurality of holes at the unit pixel areas. A resistance layer is formed on the main cathode electrode layer while being positioned at the unit pixel areas. A first insulation layer with one or more contact holes is formed on the resistance layer. A subsidiary cathode electrode layer is formed on the first insulation layer while contacting the resistance layer through the contact holes. A second insulation layer is formed on the subsidiary cathode electrode layer. The gate electrode layer is formed on the second insulation layer. A field emitter with a plurality of electron emitting members is positioned within the holes of the gate electrode layer while resting on the subsidiary cathode electrode layer. An anode electrode layer is formed on the bottom surface of the second substrate with a predetermined electrode pattern. A phosphor layer is formed on the anode electrode layer.