The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2002
Filed:
Jun. 04, 1999
Swaroop Adusumilli, Tempe, AZ (US);
Koninklijke Philips Electronics N.V., Eindhoven, NL;
Abstract
The present invention is a system and method that permits appropriate scan testing of internal components of an integrated circuit while reducing the number of external pins required to perform the scan testing. One embodiment of the present invention utilizes standard IEEE 1149.1 pins (e.g. TDO, TDI, TMS, TCK, etc.) to perform both boundary scan and full scan testing. A modified IEEE 1149.1 TAP controller generates signals to control the boundary scan and full scan operations. For example, a full scan cell facilitates full scan capture and shift operations when the TAP controller generates a full scan test mode signal and a full scan enable signal in response to inputs via the standard IEEE 1149.1 pins. In one example the scan enable signal is asserted when the TAP controller is in a shift state and the TAP controller's instruction register is loaded with a test mode instruction. A functional clock capture cycle is applied when the state machine of the TAP controller is in run/idle state.