The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2002
Filed:
Jun. 28, 2001
Efficient and robust random access memory cell suitable for programmable logic configuration control
Rafael C. Camarota, Sunnyvale, CA (US);
Adaptive Silicon, Inc., Los Gatos, CA (US);
Abstract
For a programmable Logic Array (PLA) having a nominal operating voltage, a method for ensuring reliable operation of the PLA during a configuration memory read operation comprises steps of (a) providing an intentionally weak pass gate for memory cells in the configuration memory, too weak to flip latches of the memory cells with nodes of the cells powered at the nominal operating voltage; and (b) powering the nodes of the cells with a voltage-controlled source, allowing voltage for the nodes to be reduced during write so latches may be flipped by the weak passgate, and allowing voltage to return to the nominal higher value during read, such that the weak pass gates cannot flip latches. A memory cell with such a weak passgate and operating characteristics is taught, a configuration memory using such cells, and a Programmable Logic Array with such a configuration memory.