The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2002

Filed:

Nov. 16, 2000
Applicant:
Inventor:

Glenn A. Rinne, Apex, NC (US);

Assignee:

Unitive Electronics, Inc., Durham, NC (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/11 ; H05K 1/14 ;
U.S. Cl.
CPC ...
H05K 1/11 ; H05K 1/14 ;
Abstract

Microelectronic packages include a first microelectronic substrate, a second microelectronic substrate that is oriented at an acute angle relative to the first microelectronic substrate, and first solder bumps between the first and second microelectronic substrates, adjacent an edge of the second microelectronic substrate, that connect the second microelectronic substrate to the first microelectronic substrate and that are confined to within the edge of the second microelectronic substrate. The edge of the second microelectronic substrate is adjacent the vertex of the acute angle. A third microelectronic substrate also may be provided on the first microelectronic substrate that laterally overlaps the second microelectronic substrate. Second solder bumps connect the third microelectronic substrate to the first microelectronic substrate. The second and third microelectronic substrates may be oriented parallel to one another at the acute angle relative to the first microelectronic substrate. Alternatively, second solder bumps are adjacent a first edge of the third microelectronic substrate and opposite a second edge of the third microelectronic substrate, wherein the second edge of the third microelectronic substrate is adjacent the vertex and wherein the first edge of the third microelectronic substrate is opposite the vertex.


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