The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2002
Filed:
Jan. 16, 2001
Gitu Jain, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method and apparatus for placing output signals having different voltage levels on output pins of a programmable logic device (PLD). The PLD includes a plurality of function blocks (FBs), and each FB includes one or more output pins. The output signals are organized into logical output banks (LOBs), the output signals in each LOB having a common voltage level. Each of the FBs is associated with an LOB. For each FB, one or more unplaced signals are selected for placement in the FB as a function of a number of unplaced output signals in the LOB with which the FB is associated (“current LOB”), a number of output pins in FBs associated with LOBs other than the current LOB, and a number of output pins in all FBs that are associated with the current LOB and that have no assigned output signals.