The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2002
Filed:
Feb. 18, 2000
Applicant:
Inventor:
Kanji Osari, Yokohama, JP;
Assignee:
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/13205 ; H01L 2/14763 ; H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/13205 ; H01L 2/14763 ; H01L 2/1336 ;
Abstract
An inorganic film with a double-layers structure is used as an etching mask in an EEPROM area to pattern a double-layers gate, while a thin inorganic film obtained by removing one layer of the double-layers inorganic film by etching is used as an etching mask in a CMOS logic circuit area. Therefore, the gate pattern can be formed with high precision by using a thin etching mask in the CMOS logic circuit area.
Osari, Kanji. (2002). Method of manufacturing semiconductor device having nonvolatile memory and logic circuit using multi-layered, inorganic mask (U.S. Patent No. 6417086). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6417086
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile