Structure and method of operating an array of non-volatile memory cells with source-side programming

Abstract

An array of non-volatile memory cells are arranged along rows and columns. Each memory cell has a drain region spaced apart from a source region to form a channel region therebetween. The drain region has a greater depth than the source region. Each memory cell further includes a stack of floating gate and select gate extending over the channel region. The select gate of the cells along each row are connected together to form a wordline. Each of a number of data lines is coupled to the drain regions of at least a portion of a column of cells. Each of a number of source lines is coupled to a source region of a plurality of cells along at least a portion of a row of cells. In such a memory array, a selected memory cell is biased so that a threshold voltage of the selected memory cell is increased by injection of hot electrons from a portion of the channel region near the source region to the floating gate.