Method and apparatus for transistor optimization, method and apparatus for layout design of integrated circuit, and integrated circuit

Abstract

In designing an integrated circuit, the size of a transistor is optimized together with the folding number thereof. The optimization of the size and folding number of the transistor is accomplished by using a folding model in which a plurality of folding numbers are assumed for one transistor size. In the folding model, if the lower limit value of the transistor size W is W and the height of a placement region for the transistor is H , the folding number N can be determined arbitrarily so long as W/H N≦W/W is satisfied. If the size of the transistor is optimized together with the folding number thereof by using the folding model so long as a given design constraint is satisfied, there can be designed an integrated circuit which has been improved in terms of area and performance.