The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2002
Filed:
Jul. 26, 1999
Applicant:
Inventor:
Shigeru Yamaoka, Hyogo, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 2/900 ;
U.S. Cl.
CPC ...
G11C 2/900 ;
Abstract
A test pattern generation circuit for generating a test pattern for a disturb test is provided in an SDRAM. A test pattern generated in the test pattern generation circuit is supplied to a circuit relating to a selected bank and a test pattern is supplied from a tester to a circuit relating to other bank. As more than one test can be simultaneously performed, test time can be reduced.
Yamaoka, Shigeru. (2002). Semiconductor memory device requiring performance of plurality of tests for each of plurality of memory circuits and method for testing the same (U.S. Patent No. 6415399). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6415399
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile