System and method for supporting sequential burst counts in double data rate (ddr) synchronous dynamic random access memories (sdram)

Abstract

A system and method for supporting sequential burst counts of particular utility with respect to double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) devices wherein each memory bank is divided into halves, corresponding to Even (AO =0) and Odd (AO =1) portions. Separate address busses may be provided for those bits necessary to accommodate the maximum burst length. As the column addresses are loaded, the buffers associated with the Even bus check to determine if the pad address “Y” or “Y+1” should be loaded. Loading “Y+1” is necessary to support sequential counting if the start address is Odd (AO =1). “Y” selects in the Odd and Even banks are then selected and incremented, concurrently. Nevertheless, the Even field is always “Y+1”, that is, Y =Y +1. In operation, the present invention advantageously loads the “Even” section of the bank with “Y+1” initially (if required), then the first access, and all subsequent ones, continue with no knowledge that the “Y” address in the “Even” field is different from that in the “Odd” field. By means of the load circuit disclosed herein, Odd and Even column paths are also effectively electrically the same resulting in no appreciable difference in critical timing or substantial path layout differences.