Apparatus and method for an array processing accelerator for a digital signal processor

Abstract

A data processing system for use in arrays includes a digital signal processor, a search accelerator unit and memory unit, the memory unit having a group storage locations that store the data entries of the matrix. The locations in the matrix are identified by the indices of the location. The access of the matrix by the digital processing unit typically includes an access to a series of locations at periodic intervals along a row or diagonal of the matrix. The series of data entries can include a sequence of non-neighboring matrix data entries. The search accelerator unit includes at least one pointer unit. The pointer unit in the search accelerator unit receives beginning array indices identifying the array entry. The pointer unit increments the array indices to provide the sequence of data entry indices for the matrix. The data entry array indices are converted to a series of memory location addresses. By using the search accelerator unit to provide the resulting series of memory location addresses, the digital signal processor is relieved of developing a series of non-regular addresses for memory locations. The search accelerator unit can include a size register that determines the size of the matrix to be searched and determines the increment used in searching the matrix. The invention is applied to the processing of speech signals using codebook matrices.