The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2002
Filed:
Sep. 15, 2000
Applicant:
Inventor:
Brian Lee Abernathy, Poway, CA (US);
Assignee:
Applied Micro Circuits Corporation, San Diego, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/920 ;
U.S. Cl.
CPC ...
H03K 1/920 ;
Abstract
A differential signal current-mode logic (CML) circuit is provided which provides an equal delay output. Convention differential logic CML circuits have upper stage and lower stage transistors pairs. Input signals that are provided to the lower stage are necessarily delayed with respect to inputs provided to the upper stage. The present invention provides parallel upper stage sections so that each input signal is translated to the output through the same number of transistors. Thus, the delay associated with each input signal is made equal. Specific examples of exclusive OR, OR, and AND circuits are provided.