The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2002
Filed:
Mar. 13, 2000
Hideaki Matsuhashi, Tokyo, JP;
Oki Electric Industry Co., Ltd., Tokyo, JP;
Abstract
A fabrication method for fabricating a dual-gate CMOSFET on a semiconductor substrate according to the present invention includes: implanting ions of N-type impurity for forming a deep junction source and drain in a first region on the semiconductor substrate where an NMOSFET is to be formed; performing a first annealing process for activating the N-type impurity; implanting ions of P-type impurity for forming a deep junction source and drain in a second region on the semiconductor substrate where a PMOSFET is to be formed; and performing a second annealing process for activating the P-type impurity. By performing the above processes in that order, the N-type impurity ions in the N polysilicon gate electrode of the NMOSFET are sufficiently activated, thus preventing the problem of depletion. Also, fluctuation of a threshold voltage because of penetration of the P-type impurity ions in the gate electrode of the PMOSFET can be prevented in the PMOSFET.