Direct memory access controller having on-board arbitration circuitry

Abstract

The present invention is directed to an improved direct memory access controller, having built-in arbitration circuitry, whereby multiple, identical, DMA controllers may be cascaded within a computing system, without requiring additional (i.e., separate) arbitration circuitry. In accordance with one aspect of this invention, a DMA controller is provided having a first input for connection to a DMA Acknowledge signal, and a first output for connection to a DMA Request. A second output is also provided for carrying a signal that is representative of activity of the DMA controller. In this regard, the second output may be configured to output a signal in either an Enable state or Inhibit state. If the DMA controller is active (i.e., presently controlling the transfer update among memory devices), then the second output is placed in an Inhibit state. Otherwise, the second output is controlled to be in an Enabled state. In this way, this second output is configured for direct connection to a first input of a second, similar, DMA controller device. Further, the DMA controller includes a sense circuit that is configured to detect a state of the DMA Request signal. Finally, the DMA controller includes a controller circuit that is responsive to both the first input and the sense circuit, and is configured to generate the second output.