The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 2002
Filed:
Aug. 28, 1998
Michael R. Conboy, Austin, TX (US);
Patrick J. Ryan, Kyle, TX (US);
Elfido Coss, Jr., Austin, TX (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
Techniques for controlling the flow of wafer lots in a semiconductor fabrication facility having multiple storage locations and a fabrication facility employing such techniques are provided. A process and system for controlling the flow of wafer lots within a semiconductor fabrication facility, in accordance with one embodiment of the invention, includes determining a first storage location for a wafer lot, determining, prior to moving the wafer lot, an availability condition of the first storage location based on a condition level of the first storage location and a priority of the wafer lot, and storing the wafer lot in the storage location if the location is available and storing the wafer lot in an alternate location if the storage location is unavailable. The storage location may, for example, be a stocker. In this manner, the invention may, for example, advantageously anticipate or sense bubbles or log jams of wafer lots in a fabrication facility and redirect wafer lots in order to avoid or reduce any bubble effect. This can, for example, significantly increase the throughput of wafers through the fabrication facility.