The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2002

Filed:

Jun. 14, 2001
Applicant:
Inventors:

Jeff S. Kueng, New Brighton, MN (US);

Justin J. Kraus, Chaska, MN (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 7/08 ;
U.S. Cl.
CPC ...
H03K 7/08 ;
Abstract

A circuit configured to correct a duty cycle error or vary the duty cycle of a clock signal. The circuit includes a differential amplifier or control circuit that receives differential signal inputs. At least one differential pair of transistors is connected to outputs of the differential amplifier or control circuit. Outputs of the one or more differential pairs of transistors are connected to inputs of a differential circuit. The differential amplifier or control circuit is connected to the outputs of the differential circuit. The one or more differential pairs of transistors is configured to change a DC level of at least one of the inputs of the differential circuit in order to shift a cross over point of the inputs of the differential circuit and thereby effect a duty cycle change (or correction) at the outputs of the differential circuit.


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