The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6410962 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 25, 2002

Filed:

Apr. 09, 2001
Applicant:
Inventors:

Stephen Frank Geissler, Underhill, VT (US);

Steven Howard Voldman, South Burlington, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/362 ;
U.S. Cl.
CPC ...
H01L 2/362 ;
Abstract

A method of dissipating charge from a substrate of an SOI device is provided wherein a charge dissipation path is formed in the device so that it abuts the various layers thereof. Exemplary charge dissipation paths include high conductive materials, resistive means, and field emission or arc discharge means. SOI structures having said charge dissipation path formed therein are also provided. SOI ESD circuits between SOI substrate and chip ground Vss are provided herein.


Find Patent Forward Citations

Geissler, Stephen. (2002). Structure for soi wafers to avoid electrostatic discharge (U.S. Patent No. 6410962). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6410962

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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