The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 2002
Filed:
Apr. 21, 1999
Christopher Lee Pike, Fremont, CA (US);
Advanced Micro Devices, Inc, Sunnyvale, CA (US);
Abstract
In a method for detecting defects in both processed and unprocessed (blank) wafers, a manufacturer's identification mark is used to align wafers during inspection. The wafers, are subject to an initial scan under low magnification using an inspection tool and transferred to a high magnification analysis tool for more complete analysis. Prior to scanning, the wafers are oriented using the manufacturer's identification mark. The wafers become misaligned when transferred between tools. Using the manufacturer's identification mark, the wafers are reoriented and aligned. During scanning, defects in the wafer surface are located. The location of all defects are referenced to the location of the manufacturer's identification mark. To easily find defects when a wafer is transferred from tool to tool, the manufacturer's identification mark is located and, using a software algorithm, the wafer is oriented and aligned to the mark each time it is transferred and inspected. When placed in an analysis tool, the software algorithm aligns the wafer using the manufacturer's identification mark. This allows the analysis tool to navigate directly to the desired features (i.e. defects) without wasting undue time searching for them. Furthermore, a wafer can be aligned using the mark and inspected for defects and then subjected to processing, after which the wafer is realigned using the mark and inspected again. This allows easy identification and examination of defects introduced during processing.