The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 2002
Filed:
Nov. 16, 2000
Doede Terpstra, Eindhoven, NL;
Jan Willem Slotboom, Eindhoven, NL;
Youri Ponomarev, Eindhoven, NL;
Petrus Hubertus Cornelis Magnee, Eindhoven, NL;
Freerk Van Rijs, Nijmegen, NL;
Koninklijke Philips Electronics N.V., Eindhoven, NL;
Abstract
A method of manufacturing a semiconductor device comprising heterojunction bipolar transistors (HBTs), in which method a first semiconductor layer of monocrystalline silicon ( ), a second semiconductor layer of monocrystalline silicon comprising 5 to 25 at. % germanium ( ) and a third semiconductor layer of monocrystalline silicon ( ) are successively provided on a surface ( ) of a silicon wafer ( ) by means of epitaxial deposition. Base zones of the transistors are formed in the second semiconductor layer. In this method, the second semiconductor layer is deposited without a base doping, said doping being formed at a later stage. Said doping can be formed by means of an ion implantation process or a VPD (Vapor Phase Doping) process. This method enables integrated circuits comprising npn-transistors as well as pnp-transistors to be manufactured.