Mechanism for fast access to control space in a pipeline processor

Abstract

A method for low latency access to the control space. A pipeline processor executes instructions in multiple stages including a decode stage, one or more execution, stages, and a writeback stage. A control space access instruction includes a first field containing a control register specifier and a second field containing a general purpose register specifier. The decode stage is configured to decode the first and second fields and place the decoded contents on a global operand bus. The specified control register is addressed from the global operand bus while the access instruction is in decode. In the case of a read instruction, the addressed control register places its contents on the global operand bus while the instruction remains in decode. In the case of a write instruction, the general purpose register is addressed during the execution stage and its contents placed on the global operand bus during the writeback stage such that the contents of the addressed general purpose register are moved to the addressed configuration register during the writeback stage.