The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2002

Filed:

Mar. 02, 2000
Applicant:
Inventor:

Shigenori Miyauchi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/202 ;
U.S. Cl.
CPC ...
G06F 1/202 ;
Abstract

A RAM ( ) used by the CPU comprises a work buffer ( ) and a work register ( ) for pipelined processing. The work buffer ( ) consists of the first to fourth work buffers ( to ) each of which stores information on predetermined data, e.g., a current processing on the data. When the CPU accesses the first to fourth work buffers ( to ), an address decoder performs an address conversion on the basis of a value (R ) of the work register ( ). For example, when the value (R ) of the work register ( ) is “1”, addresses (P , P , P and P ) in an address space are converted (mapped) to addresses (AD , AD , AD and AD ) of work buffers ( and ). With this constitution, in performing a plurality of data processings in parallel, the CPU can improve its operation efficiency while controlling a currently performed processing on each data.


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