The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2002

Filed:

Feb. 12, 2001
Applicant:
Inventors:

Kazuhisa Ninomiya, Tokyo, JP;

Mitsuru Sekiguchi, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract

A nonvolatile semiconductor memory device comprises a plurality of sectors each having a plurality of memory cell arrays, a controller which responds to an address signal and a control signal to activate at least one of the sectors; and a plurality of data comparing circuits provided in the memory cell arrays, respectively, the data comparing circuits each which latches a write data to be written the respective memory cell arrays and compares the write data latched and a data read out from the respective memory cell arrays to produce a comparison result. The controller activates all of the sectors when the control signal has a first logic level regardless of levels of the address signal so that write data is written into the memory cell arrays of the sectors activated. The controller activates the sectors in sequence in response to changing levels of the address signal when the control signal has a second logic level to output the comparison results from the data comparing circuits in sequence.


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