Method and apparatus for a bias generator with output current dependent on clock frequency

Abstract

An electronic circuit generates a bias current that is proportional to a frequency of a reference clock signal in a switched capacitor circuit. The electronic circuit includes a capacitive circuit selectively coupled to a transistor supplied by a voltage reference circuit. During a first phase the capacitive circuit is charged by a current from the transistor, and during the second phase the capacitive circuit is discharged to ground. The duration of each phase is related to the reference clock signal. The average current corresponds to a bias signal and is filtered to reduce ripple in the bias signal before the bias signal is received by the switched capacitor circuit. The capacitive circuit is configured with a first and second capacitor arranged in a complimentary out-of-phase configuration. During a first phase, the first capacitor is charged and the second capacitor is discharged. During the second phase, the second capacitor is charged and the first capacitor is discharged. The out-of-phase configuration reduces the size of each capacitor used for the capacitive circuit as compared to a single capacitor. The configuration also reduces ripple in the current, which reduces the size of the filter. The frequency dependant current is mirrored into the switched-capacitor circuit. In one example, the electronic circuit is implemented as an integrated circuit including “on-chip” capacitors that have inherent parasitic capacitances associated therewith. In this instance, the type and orientation of the electronic circuit capacitors should match the switched capacitor circuit capacitors such that parasitic effects track one another.