The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 2002
Filed:
Feb. 12, 2001
Helmut Fischer, Taufkirchen, DE;
Jochen Müller, München, DE;
Infineon Technologies AG, Munich, DE;
Abstract
The invention relates to a fusible link configuration in or on integrated circuits, in particular highly integrated memory chips, in which in each case one bank of fusible links (F , F , . . . ), together with an evaluation logic unit is configured beside and in association with a memory field segment. The evaluation logic unit is electrically connected to the fusible links (F , F , . . . ) and determines whether one or more of the fusible links (F , F , . . . ) is severed. One or more banks of the fusible links (F , F , . . . ) are divided up into smaller units while restricting the width(s) of the bank or banks. The units are grouped such that at least some of the fusible links (F , F , . . . ) are located beside one another transversely with respect to the width direction of the bank.