The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2002

Filed:

Jul. 13, 2000
Applicant:
Inventors:

Tarun Verma, Fremont, CA (US);

Larry Anderson, Fremont, CA (US);

Jon Long, Livermore, CA (US);

Bruce Pedersen, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/348 ;
U.S. Cl.
CPC ...
H01L 2/348 ;
Abstract

A semiconductor package including a universal substrate with interior pads, peripheral pads, and substrate traces positioned between the interior pads and the peripheral pads. The interior pads are configured for electrical interface with a first semiconductor chip. The peripheral pads are configured for electrical interface with a second semiconductor chip that is larger than the first semiconductor chip. By providing a universal substrate that can accommodate multiple die sizes, package design time and costs can thus be reduced.


Find Patent Forward Citations

Verma, Tarun. (2002). Semiconductor package with universal substrate for electrically interfacing with different sized chips that have different logic functions (U.S. Patent No. 6407450). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6407450

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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