The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 2002
Filed:
Dec. 20, 1999
Dong Shin, Taejeon-si, KR;
Keon Yang Park, Taejeon-si, KR;
Young Hwan Shin, Taejeon-si, KR;
Byung Kook Sun, Taejeon-si, KR;
Jae Heun Joung, Taejeon-si, KR;
Samsung Electro-Mechanics Co., Ltd., Kyongki-Do, KR;
Abstract
A method for manufacturing a build-up multi-layer printed circuit board is disclosed in which a YAG laser is used upon the formation of a via hole in the multi-layer printed circuit board, such that it can have the following advantages: the manufacturing process would become simple; the component packaging density and freedom for the design of the board would be improved; and a high speed of signal process would be ensured. The method for manufacturing a build-up multi-layer printed circuit board includes the steps of: forming a first printed circuit pattern on a copper clad laminate (CCL) by applying a general photo-etching process, the CCL having a copper foil on the one face thereof; stacking a resin-coated (on one face) copper foil (RCC) on the CCL with the first printed circuit pattern formed thereon, and heating and pressing this structure; irradiating a YAG laser to the board with said RCC stacked so as to form a via hole at a predetermined position by removing said RCC; carrying out an electroless and electro copper plating on the board with the via hole formed therein to form a plated layer; and forming a second printed circuit pattern on said plated layer to electrically connect the layers on which the first and second printed circuit patterns are formed.