The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2002

Filed:

Dec. 29, 1999
Applicant:
Inventor:

Takanori Nawa, Kasugai, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

A design method optimizes the dimensions (length and width) of power supply lines in a semiconductor integrated circuit. First, the power supply lines are analyzed to determine initial values for the lines. Then, a current-capacitance ratio of each of the power supply lines is calculated using the analysis results. Finally, a dimension of each of the poser supply lines is computed so that the corresponding current-capacitance ratio is within a predetermined range. The resulting power supply lines are as narrow as possible without causing a voltage drop violation or a current amount violation.


Find Patent Forward Citations

Nawa, Takanori. (2002). Method for optimizing power supply wiring in a semiconductor integrated circuit (U.S. Patent No. 6405346). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6405346

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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