Split pending buffer with concurrent access of requests and responses to fully associative and indexed components

Abstract

For a cache-coherent controller for a multiprocessor system sharing a cache memory, a split pending buffer having two components: a fully-associative part and an indexed part that can easily be made multi-ported. The associative part, PBA, include multiple entries having a valid bit and address fields, and the indexed part, PBC, includes entries including all the other status fields (i.e., the content part of the pending buffer entries). The split multi-ported pending buffer enables one request and one or more responses to be handled concurrently. Handling a request requires an associative lookup of PBA, a possible directory lookup, a possible read of PBC (in case of collision), and after processing the request in a request protocol handling unit, a possible PBA update, a possible PBC update, and a possible directory update, depending upon the cache coherence protocol implemented. Handling a response requires no PBA lookup, no directory lookup, a PBC read, and after processing the response in a response protocol handling unit, a possible PBA update, a possible PBC update, and a possible directory update, depending upon the cache coherence protocol implemented.