Digital radio receiver lock detector

Abstract

A digital radio tuner lock detector receives an in-phase (I) data signal and a quadrature (Q) data signal. The lock detector processes these signals to compute a data signal power estimate and integrates the data signal power estimate to provide a threshold signal value. The lock detector also includes a carrier frequency lock detector and a carrier phase lock detector. The carrier frequency lock detector receives the I and Q data signals and computes a frequency error signal and integrates the frequency error signal to provide an integrated frequency error signal. The carrier frequency lock detector compares the magnitude of the integrated frequency error signal to the threshold signal value to determine if frequency lock has been achieved and provides a frequency lock status signal indicative thereof. The carrier phase lock detector receives the I and Q data signals and computes a phase error signal and integrates the phase error signal to provide an integrated phase error signal. The phase lock detector also compares the magnitude of the integrated phase error signal to the threshold signal value to determine if carrier phase lock has been achieved. Carrier frequency recovery occurs first and when the carrier frequency lock detector identifies carrier frequency lock, carrier phase recovery is then performed. Once the carrier phase lock detector identifies phase lock, then accurately received data is available for signal processing. The detector may be employed in either full digital demodulators (i.e., parameter estimation and correction are performed digitally) or hybrid demodulators (i.e., parameter estimation is performed digitally and carrier frequency and phase correction are performed in the continuous time domain).