The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2002

Filed:

Sep. 24, 1999
Applicant:
Inventor:

Ken Numata, Ibaraki, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 5/08 ;
U.S. Cl.
CPC ...
G11C 5/08 ;
Abstract

A twisted bit line structure ( ) in an integrated memory circuit, and method for making it are presented. The structure is constructed by forming bit line traces ( ) on an integrated circuit substrate ( ) using phase shift lithography techniques. Using these techniques, the bit line traces are arranged with a plurality of substantially parallel bit lines trace segments ( ′) with discontinuous regions between segments of the interior pair ( ′) of traces. Thus, each “phase &pgr;” bit line trace is adjacent a “phase 0” bit line trace. A first twist connection ( ) is formed between first segments ( ′) of the center pair of said bit line trace segments at a first height above the level on which the traces are formed, and, and a second twist connection ( ) is formed between second segments ( ′) of the center pair of said bit line trace segments at a second height above the level on which the traces are formed.


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