The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 2002
Filed:
Jan. 12, 2001
Yi-Ren Hwang, Tainan, TW;
Meng-Jer Wey, Hsinchu, TW;
Faraday Technology Corp., Hsinchu, TW;
Abstract
The high-speed, low setup time, voltage-sensing flip-flop of an embodiment of the present invention comprises a master stage and a slave stage. The master stage has a data input and a clock input. The slave stage receives two signal lines from the master stage. When the clock input is low, the two input lines to the slave stage are pulled high. This turns on two transistors and precharges the inputs to the slave stage. When the clock makes a high transition, the pullup transistors in the master stage are turned off which decouples the inputs of the slave stage from the output of the master stage. At this time, if the data input is high, the A input to the slave stage is discharged. If the data input is low, the B input to the slave stage is discharged. After the two inputs to the slave stage are decoupled from the master stage, any change in the data input signal causes the inputs to the slave stage to float low since the two lines are not pulled high or low. In this way, the inputs to the slave stage are precharged and discharged on every clock cycle. This precharging results in a nearly zero setup time.