The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2002

Filed:

Aug. 07, 2000
Applicant:
Inventors:

Tae-Young Chung, Kyunggi-do, KR;

Hyung-Soo Uh, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ; H01L 2/14763 ; G03C 5/00 ; G03C 5/10 ;
U.S. Cl.
CPC ...
H01L 2/1336 ; H01L 2/14763 ; G03C 5/00 ; G03C 5/10 ;
Abstract

The present invention provides a method of forming in an insulating layer a trench that has a minimum feature size exceeding photolithographic resolution limits. The trench is formed by a two-step photolithographic process. The two-step photolithographic process defines a trench mask pattern with a rectangular or/and square shape. The first step photolithographic process defines a plurality of first patterns parallel with each other on the insulating layer. The second step photolithographic process defines a plurality of second patterns on the first patterns and on the insulating layer. The second patterns intersect the first patterns, defining the trench mask pattern. The trench mask pattern is partially etched to form a trench mask pattern with reduced feature sizes exceeding the photolithographic resolution limits. Using the trench mask pattern with reduced feature sizes, the insulating layer is etched to form the trench with a good etching profile and smaller feature sizes, thus facilitating semiconductor circuit densification.


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