Memory based on a four-transistor storage cell

Abstract

A memory organized as a two-dimensional array of data storage cells having a plurality of rows and columns. Each data storage cell has first, second, third, and fourth terminals, each data storage cell sinking a current between the first and second terminals indicative of a charge stored therein when the third terminal is at a first potential. The memory has a plurality of bit lines, one corresponding to each column. The first terminal of each data storage cell in each column is connected to the bit line corresponding to that column when the third terminal is at the first potential and each data storage cell is disconnected from that bit line when the third terminal is at a second potential. The memory also includes a plurality of column select lines and row select lines. There is one column select line corresponding to each column and one additional column select line adjacent to either the first or last column. The fourth terminal of each data storage cell in each column is connected to the column select line corresponding to that column. Similarly, there are row select lines, one corresponding to each row, the third terminal of each data storage cell in each row being connected to the row select line corresponding to that row. The second terminal of each data storage cell in each column is connected to the column select line of an adjacent column. The charge stored by each data storage cell is determined by the potential difference between the first and second terminals of that data storage cell when the third and fourth terminals of that data storage cell are held at a first potential.