The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2002
Filed:
Jun. 29, 2000
Sammy K. Brown, Los Gatos, CA (US);
George E. Avery, Saratoga, CA (US);
Andrew K. Wiggin, San Carlos, CA (US);
Samuel W. Beal, Mountain View, CA (US);
Alpine Microsystems, LLC, Campbell, CA (US);
Abstract
A plurality of integrated circuits are efficiently interconnected to improve the electrical performance of the overall system. This is accomplished by providing high speed, high density, system level interconnect, including interchip routing lines, on the integrated circuit devices, thereby reducing the routing complexity of the substrate or board. The devices are mounted directly on the board. An integrated circuit device comprises an integrated circuit region including integrated circuit elements. An interconnect layer includes an insulative material, a plurality of conductive traces, and a plurality of conductive bond pads arranged in first and second subsets. A first subgroup of the conductive traces are connected to the integrated circuit elements in the integrated circuit region and are connected to the first subset of conductive bond pads. A second subgroup of the conductive traces are electrically insulated from the integrated circuit elements and are electrically insulated from the first subgroup of the conductive traces to form a pass through. The second subgroup of the conductive traces are connected to the second subset of conductive bond pads.