The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2002

Filed:

Aug. 09, 2000
Applicant:
Inventors:

Mark K Lesher, Mohrsville, PA (US);

Douglas D Lopata, Boyertown, PA (US);

Assignee:

Agere Systems Guardian Corp., Orlando, FL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01H 3/776 ;
U.S. Cl.
CPC ...
H01H 3/776 ;
Abstract

An integrated circuit includes a pulse generator for generating a pulse of a predetermined duration. A first switch, controlled by the pulse, drives current into a fuse link when the pulse takes on a first logic level. The first switch prevents flow of current into the fuse link when the pulse takes on a second logic level. A latch is coupled to the fuse link to sense a logic level developed during the pulse. The latch may be cleared by the leading edge of the pulse. The logic level developed at the fuse link due to the driven current is latched into the latch by the trailing edge of the pulse and is indicative of whether the fuse link was blown or not blown.


Find Patent Forward Citations

Lesher, Mark. (2002). On-chip trim link sensing and latching circuit for fuse links (U.S. Patent No. 6400208). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6400208

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…